Automotive
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Tessent DefectSim
Tessent DefectSim replaces manual test coverage assessment in AMS circuits needed to meet quality standards such as ISO 26262 and provides objective data to guide improvements in DFT. Tessent DefectSim dramatically reduces SPICE simulation time compared to simulating every potential defect. |
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Tessent Diagnosis
Tessent Diagnosis uses failure data from manufacturing test, scan test patterns, and design information. With this data, Tessent Diagnosis identifies the location and classification of the defect causing the failure. Detailed analysis of devices that fail manufacturing test has been shown to greatly reduce the failure analysis effort and enables a diagnosis-driven yield analysis flow. |
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Tessent IJTAG
To manage the complex requirements of testing a heterogeneous set of embedded IP, the industry developed IEEE 1687 (IJTAG). It standardizes a language for describing the IP interface and how IPs are connected to each other. It also introduces a language that defines how patterns that operate or test the IP are to be described. IEEE 1687 draws a clear line between what must be covered by the standard and what is better left to the ingenuity of the tool developers. |
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Tessent MissionMode
The Tessent MissionMode architecture uses an IEEE 1687 (IJTAG) based network to provide system-level low latency access to all on-chip test resources for on-line test and diagnosis. At the heart of this test architecture is the Tessent MissionMode controller, which can take over the TAP signals and drive any test or diagnostic commands to any and all test IP in the IJTAG network. The MissionMode controller supports a system-level communication architecture through parallel read and write operations to and from a CPU backplane bus. |
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