Memory Test
Tessent MemoryBIST
Tessent® MemoryBIST provides a complete solution for at-speed testing, diagnosis, and repair of embedded memories. The solution’s architecture is hierarchical, allowing BIST and self-repair capabilities to be added to individual cores as well as at the top level. Tessent MemoryBIST includes a unique comprehensive automation flow that provides design rule checking, test planning, integration, and verification all at the RTL or gate level.. |
||
Tessent DefectSim
Tessent® DefectSim is a transistor-level defect simulator for analog, mixed-signal (AMS), and non-scan digital circuits. It measures defect coverage and defect tolerance. Tessent DefectSim is perfect for both high-volume and high-reliability ICs. Tessent DefectSim replaces manual test coverage assessment in AMS circuits needed to meet quality standards such as ISO 26262 and provides objective data to guide improvements in DFT. Tessent DefectSim dramatically reduces SPICE simulation time compared to simulating every potential defect. |
 |
|
|
|
|
|
