Oasys-RTL

Capacity and RunTime

Oasys-RTL brings a new approach to design creation by taking an entire chip design all the way from RTL to placed gates/macros in a single pass. Designs of tens of millions of gates can be processed in a few hours, taking an entire chip netlist to placed gates in a fraction of the time needed by tradition synthesis tools.

The large capacity is matched by blazingly fast runtimes with the ability to synthesize entire chips in a matter of a few hours, as opposed to days. The key to the high capacity and runtime is optimizing at a higher-level of abstraction, a methodology that also results in better quality of results and reduces the iterations required for design closure. Oasys-RTL can optimize designs that contain 100s of millions of gates in a single-pass synthesis run. Oasys-RTL delivers up to 10x faster synthesis time compared to traditional synthesis tools and its unique scalable architecture provides 100+ million gate design capacity to tackle the growing design sizes.

Low Power

Oasys-RTL offers a comprehensive set of power-aware synthesis capabilities including support for multi-threshold libraries, automatic clock gating, and UPF based Multi-VDD flow. During synthesis it inserts all the appropriate level shifters, isolation cells and retention registers depending on the power intent as defined in the UPF. Oasys-RTL performs dynamic and static RTL power analysis, optimization, and debug. It accepts a VCD file or variable toggle rate information, and supports programmable clock gating insertion to minimize dynamic power. Power hot spots can be highlighted in the floorplan and power reports and cross-probing between the layout and RTL helps pinpoint the root cause.

RTL Level Floorplanning

Oasys-RTL provides a breakthrough technology to create a floorplan directly from the design RTL using design dataflow and timing, power, area, and congestion constraints. Oasys-RTL considers regions, fences, blockages and other physical guidance using the advanced floorplan editing tools and automatically places macros, pins, and pads. Oasys-RTL also provides floorplan analysis capabilities for congestion, timing, static and dynamic power, DFT, and area metrics to identify issues early in the design cycle and make incremental changes. The floorplan created by Oasys-RTL can be fed forward for physical design, thereby significantly shrinking the time taken to arrive at a production floorplan for physical implementation.

Highest Quality

Oasys-RTL uses a unique placement-first method of RTL optimization. Rather than synthesizing first, then trying to optimize the gates, Oasys-RTL concurrently optimizes higher-level RTL partitions where it has a greater ability to converge on the best solution. Oasys-RTL provides better quality of results by enabling physical accuracy, floorplanning, and fast change-and-check optimization iterations that are needed to get to design closure on time.

Oasys-RTL first synthesizes the RTL into virtual physical partitions. Each partition is optimized and implemented as placed gates and if needed, the RTL is repartitioned until all top-level design specifications are met. The output of Oasys-RTL are a netlist and DEF file that provide the best starting point for place and route.

Oasys-RTL addresses the need for higher capacity, faster runtimes, improved QoR, and physical awareness by optimizing at a higher level of abstraction along with offering an integrated floorplanning and placement capabilities.