Nitro-SoC

网站首页  ꄲ  解决方案  ꄲ  Electrical & Electronics  ꄲ  IC Synthesis，Design & Verification  ꄲ  Nitro-SoC
 

Nitro-SoC Ultra Low Power Solutions

 

In addition to the Nitro Reference Flow (NRF) enabling ultra-low power implementation, Nitro-SoC provides concurrent multi-Vt optimization, power gating, retention flop synthesis, and power-aware buffering and sizing. The Nitro-SoC power-aware CTS minimizes power in the clock network and ensures a balanced clock tree with optimal power. Nitro-SoC supports the Unified Power Format (UPF), including the ability to describe design intent through power state definition tables.

  

TAT Reduction

 

  • ·New core engines for speed and QoR
  • ·Distributed and multithreaded analysis and optimization
  • ·Signoff physical verification during implementation with Calibre InRoute
  • ·Minimal ECO iterations through MCMM optimization
  • ·Signoff quality built-in timing and extraction engines
  • ·Industry’s first multi-threaded timing engine
    

 

Advanced Nodes

 

  • ·Comprehensive multi-patterning and FinFET support
  • ·Native coloring, verification and conflict resolution
  • ·DRC, double/multi-patterning, and DFM rule support for all leading foundries
  • ·Intelligent conflict double/multi-patterning resolution engine
  • ·Pattern matching and recommended rules support
  • ·Variation-aware timing and SI-driven routing
  

Highest Capacity

 

·Compact database and flexible architecture
·Ability to handle 100+ million instance designs
·Flexible abstraction capabilities including SI-ILM, HTP, and black boxes
·Unique synchronized optimization at the top-level design
·Advanced memory reduction technologies

 

  
ꂃ上一篇： 无
ꁹ下一篇： 无