Logic Test
 |
Tessent DefectSim
Tessent DefectSim replaces manual test coverage assessment in AMS circuits needed to meet quality standards such as ISO 26262 and provides objective data to guide improvements in DFT. Tessent DefectSim dramatically reduces SPICE simulation time compared to simulating every potential defect. |
|
Tessent FastScan
Tessent® FastScan™ simplifies the process of generating high-coverage compact test sets. Its ability to be applied to most any type of design makes it the most versatile ATPG solution available. Comprehensive at-speed test is critical to ensure high-quality testing. Tessent FastScan’s at-speed tests include transition, multiple detect transition, timing-aware, and critical path. |
||
 |
Tessent IJTAG
Tessent® IJTAG is the first product of its kind, bringing IEEE 1687 to life. Tessent IJTAG provides automation and features far beyond the basic implementation of the languages of IEEE 1687. It simplifies the process of connecting any number of IEEE 1687 compliant IP blocks into an integrated, hierarchical network and to communicate commands to the blocks from a single top level access point. It provides a flow in which the user does not need to know the ins-and-outs of IEEE 1687, but can leave it up to Tessent IJTAG to find the best possible solution for his IEEE 1687 compliant design. |
|
Tessent TestKompress
Tessent® TestKompress® delivers the highest quality deterministic scan test with the lowest manufacturing test cost. The solution uses a patented on-chip compression technique to create scan pattern sets that have dramatically less test data volume and reduced test time on the automatic test equipment. |
|
